Though fundamentally very different, in some cases clocking with a free-running clock is an alternative. That clock has a frequency that represents several gate-delays, and these delays in turn depend on the current core voltage. The end result is a clock close to optimal given the voltage applied to the core, and that even adjusts the clock within a single SMPS charging cycle.

A RISC-V prototype achieved almost 40% power savings: https://people.eecs.berkeley.edu/~bora/Journals/2017/JSSC17-...