You're right. What I really meant was that instructions were processed 'in order'. An uncached memory access slowed things down a particular amount and there was no way to cover the latency with other instructions.

The figure I found suggested that a 486 averages ~0.8 instructions per clock running full-tilt. That seems impossible unless one hardly ever hits memory.

I'm not 100% certain, but I think the pipelining would allow you to execute (some) register-only instructions in the x86 equivalent of a delay slot.

According to the specs, the original 80486 could read or write 16 bits per clock. That's probably on a DX - on a DX2 it's probably 2 clocks. And that's with in order execution - the bus was running at the same frequency as the CPU.