But scatter/gather is a primitive operation for SIMD, so if you want a RISC-based version of it, that's exactly what you would provide. Having dedicated instructions for specific operations (whether for crc/aes/nnp or whatever) feels like a CISC-based approach, so I think I agree with the GP.
RISC vs CISC is about the simplicity of the instruction set, not about whether it's easy to use.
And which SIMD instruction set should we be talking about? NEON-instructions or with the SVE instruction set?
And if we're talking about multiple instruction-sets designed for the same purpose, is this thing really RISC anymore? Or do you really mean "just not x86" when you say RISC ??
> But scatter/gather is a primitive operation for SIMD
Not in NEON, and therefore not in M1. AVX512 and SVE add scatter/gather instructions.
Intel/AMD's AVX has vgather instructions, but is missing vscatter until AVX512.
> Having dedicated instructions for specific operations (whether for crc/aes/nnp or whatever) feels like a CISC-based approach, so I think I agree with the GP.
Not only are there AES instructions on ARM, but there's also SHA-instructions. The mix-columns step of AES more or less demands dedicated hardware if you want high-speed today, so everybody implements that as a hardware specific instruction.
What RISC is about in today's context is somewhat hazy and there are lots of views and opinions about it. RISC was a branding of a shift that happened in the 70s and 80s.
It was a time of tight transistor budgets, and there was a make-or-break sweet spot of instruction set size and complexity that could be hardcoded in the ~100k transistors (vs microcoded[1], as was the norm).
IMO the fundamental idea was that you should optimize the instruction set for your applications to a certain extent, while still keeping it coherent for humans and stable across processor generations.
RISC still gives ease of use weight, without this your instruction set might be a cryptic machine learning box of mystery operations with bizarre temporal/hidden state semantics (think delay slots but much much worse) that gets rebooted on every CPU release.
RISC vs CISC is about the simplicity of the instruction set, not about whether it's easy to use.