Yes, addition is annoyingly slow due to carry propagation. But a problem with the parity flag is that it is computed on the result of your arithmetic operation, so it add another big delay to every operation. The other problem is that it adds a lot of circuitry (by 1970s standards).
Yeah agreed -- though that's what I meant about the zero flag: NOR instead of XOR combinatorial complexity, but same prop. delay critical path, only simpler circuits per bit if purely NMOS or PMOS! :)
I think the 1970s Intel were doing MOSFETs then?
Technically parity could become a stable value before the zero flag could! ;)
Oh but I did forget that a single multiple input NOR could be large but without exponential amounts of gates
